IMPROVING SECURITY IN TERNARY-BASED SOFT ERROR RESILIENT SRAM CONTENT ADDRESSABLE MEMORY USING CHECKSUMS \

Authors

  • Devarakonda Chandana, Lavanya Repaka, Uppunutula Venu, Kothapalli Aravind, Madishetty Nikilesh Kumar

Keywords:

Examples of addressable memory include soft errors, FPGAs (field programmable gate arrays), TCAM (ternary content addressable memory), SRAM (static random-access memory), and addressable memory.

Abstract

Open flow and packet classification applications in Software Defined Networking (SDN) (FPGAs) employ Ternary content addressable memory (TCAM) based on static random access (SRAM) on field programmable gate arrays. SRAM-based TCAMs will therefore be crucial to all FPGA-based systems as they will improve search speed, shorten critical path time, and lessen soft error vulnerability. In conclusion, SRAM-based TCAM will save money and time by identifying single bit parity flaws with little crucial route overhead. This method achieves low reaction time error correction by using a binary encoded TCAM table-maintained SRAM based TCAM for updates. The intended work for this article will demonstrate SRAM-based TCAM with error detection and correction in the 1024x40 size, along with enhanced security through the use of the Checksum technique. Ultimately, this project demonstrated performance in terms of area, latency, and power after being constructed in Verilog HDL and synthesised on a Xilinx Vertex 5 FPGA.

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