MAXIMIZING TEST COVERAGE THROUGH AREA-EFFICIENT BUILT-IN SELF-TEST (BIST) DESIGN AND SIMULATION

Abstract

In modern integrated circuit (IC) design, ensuring both functional correctness and reliability is paramount, especially as devices become increasingly complex. Built-In Self-Test (BIST) techniques have gained popularity as an efficient means to automate testing and improve the diagnostic capabilities of ICs. However, a significant challenge in the implementation of BIST is optimizing both area efficiency and test coverage, as traditional methods often require trade-offs between these two critical factors.