VLSI Architecture for Turbo Decoder using MAP Algorithm for Enhanced Error Correction in Communication Systems

Abstract

Turbo codes are highly effective error correction codes, utilized in communication systems due to their superior error correction capabilities. This study introduces a Very Large-Scale Integration (VLSI) architecture aimed at enhancing error correction through the development of a Turbo decoder. The decoder integrates interleavers, deinterleavers, and soft-in-soft-out decoders, all of which utilize the Maximum-a-Posteriori (MAP) algorithm. The MAP algorithm optimizes the error correction procedure, significantly reducing the number of iterations required for decoding transmitted information bits. The encoder side of the system utilizes a pseudorandom interleaver along with two recursive convolutional encoders. This method enhances the encoding procedure, thereby increasing the overall reliability and efficiency of Turbo codes within communication networks.