ADDRESS-PREDICATED SRAM ARCHITECTURE: DESIGN AND IMPLEMENTATION STRATEGIES

Abstract

The address-based SRAM architecture that serves as the foundation for this study allows for error-free and fast memory processing. The main objectives of this project are to improve system performance and reduce delays. Before transferring the data to the SRAM control circuit block, BIST first checks the input. In order to provide accurate information, CRC will identify and correct any errors in the data it receives. The address control unit uses the row and column decoders to decode data addresses. A row decoder and a column decoder with a column format are used to decode the data. Finally, the data from the row and column will be saved in an SRAM array. This data will be subject to read and write activities. This is replicated using Xilinx technology. The simulation's findings demonstrate that an efficient output in terms of area and latency is achieved.