Energy-Efficient Dual-Edge Flip-Flop Design Using Single-Transistor Clocked Buffer in 22nm FD-SOI CMOS
DOI:
https://doi.org/10.47750/Keywords:
Flip-Flop (FF) Optimization, Dual-Edge Triggering (DET), Low-Power Design, Single-Transistor Clocked Buffer (STCB), Clock Redundant Transition Reduction.Abstract
In the age of artificial intelligence (AI) and graphics processing units (GPUs), the flip-flop (FF) has emerged as one of the processor's most power-hungry elements. A innovative single phase-clock dual-edge-triggering (DET) FF employing a single-transistor clocked (STC) buffer (STCB) is suggested as a solution to this problem.
